The present disclosure relates to the field of semiconductors, and in particular, to three-dimensional semiconductor memory devices and a method of fabricating the same.
In the case of typical two-dimensional or planar semiconductor devices, integration may be determined by the area occupied by a unit memory cell, which can be related to the level of fine patterning technology used to form those cells. The expense associated with the processing equipment used fine patterning may, however, limit the integration for two-dimensional or planar semiconductor devices.
To overcome such a limitation, three-dimensional (3D) semiconductor devices, including three-dimensionally-arranged memory cells, have been proposed. There may be, however, significant manufacturing obstacles in achieving low-cost, mass-production of 3D semiconductor memory devices, particularly in the mass-fabrication of 3D devices that maintain or exceed the operational reliability of their 2D counterparts.